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Figure 7.28
Major data paths in a generic multiple-issue processor
(VLIW processor). |
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Figure 7.28 shows the data paths for a generic multiple-issue machine. The extensive use of register ports provides simultaneous access to data as required by a VLIW processor. This suggests the register set as a processor bottleneck. Dynamic multiple-issue processors can also be implemented as shown in Figure 7.28, but usually such processors use multiple buses connecting the register set and functional units, and each bus services multiple functional units. This may limit the maximum degree of concurrency, but it can also significantly reduce the required number of register ports. |
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The issue of detection of independence within or among instructions is theoretically the same regardless of whether the detection process is done statically or dynamically (although the realized effect is quite different). In the next sections, we review the theory of instruction independence and especially look at dynamically scheduled multiple-issue processors. Processors that decode but one instruction per cycle, yet allow instructions to execute simultaneously or out of order, must generally obey the same rules of instruction independence as multiple-issue machines; therefore, we treat these machines as a degenerate type of multiple-issue machine. |
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7.6 Out-of-Order and Multiple-Instruction Execution |
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In chapter 4, we looked at pipelined processors that are constrained to: |
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1. Decode at most one instruction per cycle. |
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2. Execute each instruction in the same sequential order that it appeared in the program representation. |
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