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Simple pipelined processors use an in-order pipeline organization; that is, the execution of each instruction (the PA or EX cycles) is performed in exactly the same order as it appeared in the dynamic sequence of instructions in the program. This rule is followed even though instructions may be independent of one another. The advantage of such a restricted pipeline organization is that anomalous events such as interrupts, etc., can be associated with particular instructions, and, further, no storage resource is affected subsequent to an interrupt. Consider the following example: |
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If the second instruction completes its execution and alters the state of the registers before the first instruction completes execution, the instructions have executed out of sequential order. Now the first instruction creates an interrupt at the conclusion of its execution, and it is impossible to restore the machinepreserve its state as it was at the time of interruptionsince the second instruction has already altered the contents of the processor registers. |
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It may be possible to detect an interrupt early enough to allow the concurrent execution of two instructions: |
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In this case, the two instructions complete at exactly the same time, but if an interrupt is caused by instruction 1, it may still be possible to ''kill the clock"i.e., suppress the sampling of the final results into the registers and allow recovery of the machine as it would have been if only instruction 1 had executed. Multiple instruction execution, in practice, is usually limited by the number of ports to the registers, and resource limitations simply prevent the writing of multiple results simultaneously to a single register set. Multiple instruction execution, however, might still occur in situations where the architecture supports both general-purpose (integer) registers and floating-point registers as distinct storage entities. In such a case, even if the interrupt signal could not be generated soon enough to allow absolute sequential instruction execution, there is usually little damage done, since the sequential state of both the floating-point registers and the fixed-point registers is preserved. |
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Instructions can depend on preceding instructions for source operands. For purposes of this discussion, we adopt an instruction format notation that is similar to a three-address L/S type architecture: O P D S1,S2. Such an instruction has the following effect: |
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OP D, S1, S2. |
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