|
|
|
| Table 7.4 Some superscalar processors (based on a study by N. Ghazal). |
| | (a) Chip Features of Processors |
| | Characteristic | RS/6000 | SuperSparc | DEC Alpha | Intel Pentium | Motorola/IBM Power PC | H-P PA RISC 7100 | | Chip configuration | 3 (processing chips), 1 (mem control), and I (I/O control) | Single chip | Single chip | Single chip | Single chip | Single chip | | Technology | CMOS, 1mm | BiCMOS, .8mm | CMOS, .75mm | 0.6mm BiCMOS | 0.6mm CMOS | 0.8mm CMOS | | Die size | 161mm2, largest chip | - | 233.5mm2 | 163 mm2 | 120 mm2 | 202 mm2 | | No. of Transistors | 3.5M | 3.1M | 1.7M | 3.3M | 2.8M | 850K | | Cycle Time | 3340 ns | 20 ns | 5 ns | 10 ns | 15 ns | 10 ns |
|
|
| (b) Processor Organization Features |
| | Feature | RS/6000 | SuperSPARC | DEC Alpha | Intel | Motorola | H-P | | Prefetch I Buffer Size | 12-entry | 12-entry | 8-entry | | 8-entry | | | Issue Rate (max per cycle) | up to 4 | up to 3 | 2 | 2 | 3 | 2 | | Instruction Window config. | Central | Central | Central (scoreboard) | Central | Central | Central | | Data Dependency Resol. | Interlocks (renaming for FP ops) | Interlocks | Interlocks | Interlocking | Interlocking (some renaming) | Interlocking | | Branch Policy | Static | Dynamic | Static/dyn. | Dynamic | Static | Static | | Branch Technique | Predict in-line (early CC set) | default: Predict in-line | default: Predict in-line | BTB with history bits | Backward branch predicted taken | Backward branch predicted taken | | Exception Handling | Precise | Precise | Imprecise on arithmetic exc. | | | |
|
|
|