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Figure 1.23
Paging process. |
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L1those localities (called lines) of L1 that have been recently referenced by the program. Thus, the overall action by the system consists of the generation of a virtual effective address, its translation into a real address (a main memory address), and the use of this real address to access the T0 table to find the entry in the cache for the desired value. |
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Paging and caching are the mechanisms to support the efficient management of the memory space. Caches are discussed in detail in Chapter 5. Paging is the mechanism by which the operating system brings fixed-size blocks (or pages)a typical size is 4KBinto main memory. Pages are fetched from backing store (usually disk) on demand (or as required) by the processor. When a referenced page is not present, the operating system is called and makes a request for the page, then transfers control to another process, allowing the processor resources to be utilized while waiting for the return of the requested information. |
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Figure 1.23 shows a simplified paged memory access. The resultant address (the "real address") is used to access the cache and main memory. The loworder (least significant) 12 bits address a particular location in a 4,096-byte page. The upper bits address a page table (in memory) that (1) determines whether this particular partial page lies in memory and (2) translates the upper address bits if the page is present. |
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1.7 Virtual to Real Mapping |
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Usually, the tables performing address translation are in memory, and a mechanism for the translation called the translation lookaside buffer (TLB) must be used to speed up this translation. The TLB is a simple register system usually consisting of between 64 and 256 entries. Several of the bits of the virtual address are used as an address into this table. The entry in the table contains the real address, the real upper portion of the physical |
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