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Figure 1.22
Memory space. |
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Latency is the time for a particular request to be completed. Bandwidth refers to the number of requests supplied per unit time. In order to provide large memory spaces with desirable access time (latency) and bandwidths, modern memory systems employ multiple levels of storage (Figure 1.22). Smaller, faster levels have greater cost per bit than larger, slower levels. If there are n levels in the storage hierarchy, then the levels may be ordered by their size and access time from S0, t0 for the smallest, closest level to Sn-1, tn-1 for the largest level. The goal of a good memory system design is to provide the processor with an effective memory space of Sn-1 with an access time close to t0. How well this goal is achieved depends on a number of factorsthe physical characteristics of the device used in each level as well as the behavioral properties of the processes being executed. |
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Typically, the actual physical memory space consists of a three-level hierarchy consisting of a cache (L0), a main memory (L1), and a disk or backing storage (L2), which contains the entire virtual memory space. Typical size (S) and access time ratios (t) are: |
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Associated with both the L0 storage (the cache) and the L1 storage (main memory) are the corresponding tables T0 and T1. T1 contains the working set of S2 (the disk)those disk localities that have been recently referenced and are contained in main memory [25, 69]. T1 is the same as the page table shown in Figure 1.23. T0 is completely managed by the hardware in a way transparent even to the operating system, and it contains a working set of |
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