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Page 446 where Qc is the expected number of denied requests per module, and m is the number of modules. Then m Qc = n - B, as discussed in chapter 6. If we allow bypassing, we will require additional buffer entries and additional control. Typically, an entry could include: Request source id. Request source tag (i.e., VR number). Module id. Address for request to a module. Scheduled cycle time indicating when module is free. Entry priority id (assuming more than one request can be bypassed). While some optimization is possible, it is clear that large bypassed request buffers can be complex. 7.3.3 Gamma (g)-Binomial Model We now develop the g-binomial model of bypassed vector memory behavior. Assume that each vector source issues a request each cycle (d = 1), and that each physical requestor in the vector processor has the same buffer capacity and characteristic. If the vector processor can make s requests per cycle, and there are t cycles per Tc, we have: This is the same as our n requests per Tc in the simple binomial model, but the situation in the vector processor is more complex. We assume that each of the sources s makes a request each cycle and each of its g -buffered requests also makes a request. Depending on the buffer control, these buffer requests are made only implicitly. The controller "knows" when a target module will be free and therefore schedules the actual request for that time. From a memory modeling point of view, this is equivalent to the buffer requesting service each cycle until the module is free. Thus, we now have: Total requests per Tc = t s + t s g = t s(1 + g) = n(1 + g). This can be substituted into the simple binomial equation:
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