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Figure 7.18
Vector memory
requirements.
In this
illustration, 3
operands are
read and 1 is
written each
cycle. Since the
supply of
operands from
memory should
balance their
use, memory
must keep up
with this rate, or
limit
performance. |
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Figure 7.19
Bypassed vector requests held in a buffer of size TBF. |
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An associated issue is the degree of bypassing or out-of-order requests that a source can make to the memory system. Suppose a conflict arises: a request is directed to a busy module. How many subsequent requests can the source make before it must wait? Assume each of s access ports to memory has a buffer of size TBF/s (Figure 7.19). This buffer holds requests (element addresses) to memory that are being held due to a conflict. For each source, the degree of bypassing is defined as the allowable number of requests waiting before stalling of subsequent requests occurs. |
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From a modeling point of view, this is different from the simple binomial or the d-binomial models. The basic difference is that the queue awaiting service from a module is larger by an amount g, where g is the mean queue size of bypassed requests awaiting service. Note that the average queue size (g) is always less than or equal to the buffer size: |
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g < TBF/s, |
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since g cannot exceed the size of the physically implemented buffer. (Although, depending on the organization of the TBF, one source buffer could ''borrow" from another.) |
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With or without request bypassing, there is a buffer between the s request sources and the m memory modules (Figure 7.19). This must be large enough to accommodate denied requests (no bypassing), i.e.: |
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Buffer = TBF > mQc, |
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