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Figure 7.17
Vector memory. |
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An example of this design situation is: |
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LD.V VR1, loading VR1 for later use
LD.V VR2, loading VR2 for later use
ST.V VR3, clearing VR3 for later use
OP.V VR4, VR5, VR6 using values previously fetched
LD.V VR5,
LD.V VR6,
ST.V VR4, using registers prepared above
OP.V VR3, VR1, VR2. |
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The first four instructions are executed concurrently; then the next four instructions are executed. |
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We overlap the operand fetching and storing with vector execution. We fetch the operand for the next executable vector operation at the same time we execute the current operation. |
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Three concurrent operand accesses to memory are a common target for a vector processor, but they can significantly increase the cost of the memory system. Some systems limit concurrent access to two operations, hoping that it will suffice for most cases. Of course, chaining may require even more accesses, as shown in Figure 7.18. |
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