|
|
|
|
|
|
|
Figure 7.9
Types of vector operations and some examples. |
|
|
|
|
|
|
|
|
(a) Vector operation: VR OP VR -> VR |
|
|
|
 |
|
|
|
|
VADD |
|
|
|
|
|
|
|
|
VSUB |
|
|
|
|
|
|
|
|
VMPY |
|
|
|
|
|
|
|
|
VDIV |
|
|
|
|
|
|
|
|
VAND |
|
|
|
|
|
|
|
|
VOR |
|
|
|
|
|
|
|
|
VEOR |
|
|
|
|
|
|
|
|
(b) Compare (VCOMP): VR VCOMP VR -> Scalar |
|
|
|
|
|
|
|
|
V1 VCOMP V2 -> S |
|
|
|
|
|
|
|
|
S(i) bit is ''1" if V1.i > V2.i |
|
|
|
|
|
|
|
|
Test (VTEST): V1 VTEST CC ->Scalar |
|
|
|
|
|
|
|
|
S(i) bit is "1" if V1.i satisfies CC |
|
|
|
|
|
|
|
|
CC is the condition code specified in the instruction |
|
|
|
|
|
|
|
|
Accumulate (VACC): VACC: S (V1 * V2) -> S1 |
|
|
|
|
|
|
|
|
VR VACC VR -> Scalar |
|
|
|
|
|
|
|
|
(VEXP/VCPRS): VR OP S -> VR |
|
|
|
|
|
|
|
|
Expand : Suppose S = 1 0 1 0 |
|
|
|
|
|
|
|
|
V1=1.1, 1.2, 1.3, 1.4 |
|
|
|
|
|
|
|
|
then V1 VEXP S = 1.1, 0, 1.2, 0, |
|
|
|
|
|
|
|
|
Compress : Suppose S = 1 0 1 0 |
|
|
|
|
|
|
|
|
V1=1.1, 1.2, 1.3, 1.4 |
|
|
|
|
|
|
|
|
then V1 VCPRS S = 1.1, 1.3, |
|
|
|
|
|
|
|
|
Finally, there are vector expand and compress operations, which take logical vectors and apply them to elements in vector registers to create a new vector value (see Figure 7.9). The expand and compress operations are taken from the APL language [146], where they were originally introduced. |
|
|
|
|
|
|
|
|
When a vector operation is done on two vector registers that contain contents of unequal length, some convention must be established for producing the result. The obvious convention is to specify a vector length in each vector instruction. An alternative specifies that the unused elements of the vector contain zero, the zero is applied to the other vector element, and the result is as defined. Another convention (Figure 7.10) is to establish the invalid contents symbol for all entries in a vector register that have not been explicitly stored into. This is akin to NAN in the IEEE floating-point standard, and the result is also NAN regardless of what the contents of the other register were. |
|
|
|
|
|
