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Figure 7.10
Padding out short vectors with NAN ("not a
number") representation. |
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Figure 7.11
Vector address generator for VLD/VST. |
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7.2.3 Vector Processor Implementation |
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It is clear from the foregoing that the vector extension to a conventional processor requires a considerable amount of additional control and hardware. Figure 7.11 illustrates a vector address generate extension to a conventional processor. In many cases, as in the case shown, the vector register can bypass the data cache. The data cache is used solely to contain scalar values. Since particular values contained in a vector may be aliased as a scalar and stored in the data cache, all vector references to memory must be checked against the contents of the data cache. Hits invalidate the current value contained in the data cache and force memory update if required. Additional control, either in hardware or software, must be present to ensure that scalar references from the data cache to memory do not inadvertently reference a value contained in a vector register. |
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In earlier days, a number of vector processors were built that directly referenced main memory (i.e., without the use of vector registers). This had the advantage of accommodating vector operations of arbitrarily long vector length. However, the problem of accessing memory with addresses that differ by a fixed stride, or amount, may cause severe memory congestion |
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