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well suited for anticipatory cycle timing because the sequence of actions in the pipeline is predefined. Figure 7.8 shows an anticipatory cycle functional unit for our previous example. |
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7.2.2 Vector Instructions/Operations |
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As most modern vector processors are organized about vector registers, we assume that the vector instruction set is an L/S type instruction set that executes functional operations from the registers, but with the result going to the registers. The vector load and vector store (also referred to as scatter and gather instructions) asynchronously access memory. Functional vector operations cannot use a vector register until any pending vector load from or vector store to that register is completed. |
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Generic vector operations include the obvious arithmetic operations: vector add, vector multiply, and vector divide. They also include a series of operations that either produce or use a logical vector as an argument. For example, the operation vector compare (Figure 7.9) may take two vector operands and produce a bit-vector result. The logical one indicates a match or that the compare was satisfied; a logical zero indicates otherwise. The result of this vector operation may be stored in a vector register or, in some machines, in a scalar register as a sequence of bits. This latter approach provides more efficient use of the relatively small number of vector registers that are usually available. The class of such instructions includes the following: |
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Another type of vector operation also posts its result in a scalar register. This is called a vector accumulate operation, in which the sum of products is accumulated in a particular scalar register: |
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This equation corresponds to an inner product of two vectors. |
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The class of logical vector instructions including compare is important in the vector processor. Generally, the vector instructions do not set the condition code in the program status word after each operation. The programmer does not wish to interrupt the flow of vector operations by specific tests for arithmetic conditions, which would disrupt the execution rate of the vector operations; rather, after the vector operation is complete, a compare condition instruction can be issued that compares the contents of each of the elements in the vector register to a particular condition and returns a logical vector indicating the elements in the vector that match the specified condition. |
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The results of the compare operation can be contained in a general scalar register or in a special vector mask register associated with each vector register. |
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