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Figure 7.6
For logically independent vector instructions, the number of access
paths to the vector register set and vector units may limit performance.
If there are four read ports, the VMPY can start on the second cycle.
Otherwise, with two ports, the VMPY must wait until the VADD
completes use of the read ports. |
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Figure 7.7
While independent VLD and VADD may proceed concurrently (with
sufficient VR ports), operations that use the results of VLD do not
begin until the VLD is fully complete. |
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Figure 7.8
Anticipatory cycle functional unit. |
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