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8. For a copyback cache (CBWA) with memory system as specified: |
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(a) Compute Tline access for Ta = 200 ns, Tc = 100 ns, m = 8, Tbus = 25, and L = 16. |
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(b) Repeat for m = 2 and m = 4. |
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(c) Suppose nibble mode (v = 4) is now introduced, Tv = 50 ns and m = 2. Compute Tline access. |
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9. For a copyback cache (CBWA) and w = 0.5 using the memory system of 8(a), compute Tm.miss, Tc.miss, and Tbusy for: |
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(a) Unbuffered line transfers starting at line address. |
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(b) Write buffer, line transfers starting at line address. |
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(c) Buffered transfers with wraparound load. |
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10. In problems 9 and 8(a), if the cache miss rate (assume 1 reference per cycle) is 0.03 and processor peak performance is one instruction every 25 ns cycle, what is the effect on performance of each transfer strategy in problem 9? Ignore I/O. |
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11. Now the processor in problem 10 is to use a write-through cache (WTNWA). The fraction of data writes is 0.16. Using the d-binomial model, compute the overall processor performances. |
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12. When memory is implemented using DRAM organized as 2k´ 4, the failure of a single chip can result in errors of up to four bits. Devise an error correction scheme for device failure. Detail the scheme for m = 16. Hint: think of the memory as if it were four separate 2k´ 1 submemories. |
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13. A processor without a cache accesses every t-th element of a k-element vector. Each element is one physical word. Assuming Ta = 200 ns, Tc = 100 ns, and Tbus = 25 ns, plot the average access time per element for an 8-way, low-order interleaved memory for t = 1 to 12 and k = 100. |
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14. A memory system must support an average of 75 MAPS. Using the open MB/D/1 model, find an appropriate degree of interleaving and determine the mean queue size, given a memory service time of 100 ns. To ensure the Prob {overflow} < 1%, what should the total buffer size be if (a) the Chebyshev bound is used and (b) the M/M/1 bound is used. |
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15. You are to design the memory for a 50 MIPS processor (1 CPI) with one instruction and 0.5 data references per instruction (no cache). The memory system is to be 16MB. The physical word size is 4B. You are to use 1M ´ 1b chips with Tc = 40ns. Draw a block diagram of your memory, including address, data, and control connections between the processor, DRAM controller, and the memory. Detail what each address bit does. If Ta = 100 ns, what are the expected memory occupancy, waiting time, total access time, and total queue size? Discuss the applicability of the open-queue model in the analysis of this design. |
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