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16. A simple 1 MIPS processor (1 CPI, 2 refs/I) shares a memory with a simple DMA unit which transfers 1 data word to memory every 1 msec. The memory cycle time is the same as the processor cycle time. The memory system is not interleaved and has an access time of 500 ns. Use the simple binomial approximation to find the achieved utilization (Bw) and the expected waiting time. What is the effective processor MIPS? Is the simple binomial appropriate for this system? |
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17. Repeat study 6.2 with IF/cycle = 0.5, DS/cycle = 0.3, DS/cycle = 0.1, and m = 8. |
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18. For study 6.3(a), assume that the miss rates of the CBWA cache for several possible line sizes are: 16B line = 0.03, 8B line = 0.07, 32B line = 0.02. Which line size would perform best? |
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19. For study 6.3(d), plot relative processor performance as a function of the I/O traffic rate for I/O rates from 0.01 to 0.20. Comment on the sensitivity of memory system performance to I/O traffic. |
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20. Repeat study 6.4 for Ta = 280 ns, Tc = 150 ns, and Tbus = 40 ns. |
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21. A 25 MIPS processor with 1 CPI makes two distinct types of requests to memory: word and block requests. If word requests occur at an expected rate of one per instruction, and block requests occur at an expected rate of 0.2 per instruction, find the effective request rate ls. Assume Ta = 200 ns, Tc = 100 ns, and Tbus = 40 ns, m = 8, and blocks are 8 words. Find the effective service time (Ts), the coefficient of variance, and the effective offered occupancy (r). Use the open-queue M/G/1 model to compute the expected waiting time and the expected number of requests in the queue. Should the open-queue model be used for this analysis? |
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