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3. Design a SECDED (Hamming type) coding scheme for a memory with data word size of 18 bits. Show placement of each check bit and give logic equations for its action. |
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4. A pipelined processor has a peak performance of 40 MIPS (decoding one instruction per cycle). It creates 0.90 instruction references/instr, 0.30 data reads, and 0.10 data writes per instruction. The memory system has: |
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Suppose it is possible to partition memory so that instruction references go to instruction memory and data references go to data memory. No cache is used. |
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Using the open-queue model, compute: |
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(a) The allocation of modules to instruction and data. |
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(b) Effective Tw per reference (overall). |
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(c) Queue size. |
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(d) Comparison to a single integrated (I and D) memory system (select m, a power of 2) using the same model. |
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5. Suppose two processors (in a multiprocessor system) make a total of exactly two references to memory every memory cycle (Tc = 100 ns). The memory consists of eight low-order interleaved memory modules with Taccess = 120 ns. Find: |
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(a) Expected waiting time (Tw). |
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(b) Total access time. |
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(c) Mean total number of queued (waiting) requests. |
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(d) Offered memory bandwidth (references/sec). |
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(e) Achieved memory bandwidth (references/sec) according to above model. |
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(f) Achieved memory bandwidth using Strecker's model. |
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6. The processor defined in problem 4 now uses an integrated memory system of eight modules. |
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Compare performance (B, Bw, Qt, and Tw) projections based on: |
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(a) Hellerman's model. |
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(b) Strecker's model. |
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(c) Open-queue model. |
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(d) Simple closed binomial model. |
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Compute achieved bandwidth, buffer size, and Tw for each; state all assumptions. |
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7. Evaluate the processor defined in problem 4 with single integrated memory and m = 8, using the d-binomial model. Find the achieved processor performance. |
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