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L. Kleinrock. Queueing Systems. J. Wiley and Sons, 1975. Two volumes. |
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H. Kobayashi. Modeling and Analysis: An Introduction to Systems Performance Evaluation Methodology. Addison Wesley, Menlo Park, CA, 1978. |
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F. Baskett and A. J. Smith. Interference in multiprocessor computer systems with interleaved memory. Communications of the ACM, 19(6):327334, June 1976. |
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B. R. Rau. Program Behavior and the Performance of Memory Systems. PhD thesis, Stanford University, July 1977. |
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D. Y. Chang, D. J. Kuck, and D. H. Lawrie. On the effective bandwidth of parallel memory. IEEE Transactions on Computers, C-26(5):480489, May 1977. |
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1. A 32-megabyte memory module is implemented with a 4M´ 1b chip, with nibble mode. The memory module has the following specifications: |
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40 ns up to four accesses, |
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There are additional memory system delays of: |
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(a) What is the memory system access time? |
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(b) What is the maximum memory data bandwidth (bytes per second) from four modules (m = 4, each module with nibble mode) with random address request? Assume that there are multiple buses and ECC units so that they do not limit. |
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(c) Repeat (b) for sequential requests. Show how each module is accessed (i.e., which address bits are used for each function). |
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2. If the four module memory system of problem 1 were now implemented with page mode and Tpage = 40 ns: |
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(a) How could this be used effectively in a memory design? |
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(b) Describe in detail under what conditions this would perform better than an equivalent system using nibble mode. |
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