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(d) Tenured split bus (width 16B): |
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Bus transaction time: 1 cycle. |
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Cases (c) and (d) are interesting, since now the bus capacity exceeds the memory bandwidth. (4w in 8 cycles for memory, 4w in one cycle for the bus (case d).) In both of these cases, the "bus"-memory situation is better modeled as a shared memory and not as a shared bus, as that is where the contention will develop. In handling these cases, the analysis will simply add the bus time to the memory access time, and ignore bus contention. |
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The models for n processors accessing a bus are: |
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(1) The simplest model is the previously discussed null binomial: |
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Prob (processor does not access bus) |
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Prob (n processors do not access bus) |
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Bus bandwidth = Bus B(r,n) |
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and the achieved bandwidth per processor (ra) is: |
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(2) Bus model with request resubmission. |
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This is a more complex analysis, and requires an iterative solution. There are several solutions [139, 204, 205, 307, 316], each providing (roughly) the same result. We outline the solution provided by Hwang and Briggs [139]. |
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This solution is based on a two-state (A, acceptedW, wait) request model. Requests are accepted with probability PA. |
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