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In the following, we assume that each request occupies the bus for the same service time (e.g., Tline access). Even if we have two different types of bus users (e.g., word request and line requests on a single line, or (dirty) double line requests), most cases are reasonably approximated by simple computation of the per-processor average (offered) bus occupancy. |
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The processor time is the mean time the processor needs to compute before making a bus request. Of course, it is possible for the processor to overlap some of its compute time with the bus time. In this case, the processor time is the net unoverlapped time between bus requests. In any event, r < 1. |
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The nature of the bus transaction depends on the bus structure. Multiple bus users must arbitrate for access to the bus in any given cycle. Thus, arbitration can be part of the bus transaction (i.e., request cycle followed by ack cycle) or it can be performed by adding bus control lines and associated logic. |
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Buses may be uni-or bidirectional, or split (address + data). The unified bus is occupied with both address and data; the split has separate buses for each function. |
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Finally, the buses may be tenured. This refers to buses that are occupied only while delivering addresses or data. Such buses assume the receivers buffer the messages and create separate address and data transactions. |
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Suppose we have a bus with transmission delay of one processor cycle and memory with 4 cycle access. Memory requires an additional 3 cycles to transmit a line. (M = 1 with page mode.) |
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(a) Simple bus. This might have the following bus transaction time: |
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(b) Bus with arbitration support: |
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