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		6.8.8 Write-Through Cache Example



		Assume WTNWA strategy and word-buffered I/O, so that only read misses access lines in memory. Queueing delays occur only when a write buffer is introduced or when I/O effects are taken into account. In the following study, we analyze some typical cases.



		Study 6.4 Evaluating Write-Through (WTNWA) Caches



		Assume we have determined that our processor traffic is 0.8 reads per cycle and 0.2 writes per cycle. Then, on the basis of read traffic, we determine that our cache has a miss rate of 0.024 misses per reference.



		The cache is configured as:



		Line size



		=



		16^B



		Physical word size



		=



		4^B



		and the memory is configured as:



		T_a = 120 ns, = T_c = 100 ns, T_bus = 40 ns, m = 2.



		We compute the cache miss delay for:



		(a) No fetch bypass, no write buffer, no I/O effects, ignoring write traffic contention in effective processor performance.



		This is case 1 in our analysis.



		and from study 6.3:



		T_{write interference}



		=



		260 ns



		T_miss



		=



		T_c.miss + T_{write interference}



		=



		281 ns.



		(b) Same as (a), but now including the effects of memory write contention.



		As with study 6.1(b),



		m



		=



		2,



		n



		=



		0.6,



		d



		=



		0.2,



		B(2, 0.5, 0.2)



		=



		0.54.

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