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Page 409 The processor request rate (MAPS) and its corresponding MIPS rate must decrease by a factor of: This decrease is not related to (and hence is in addition to) read cache misses and Tinterference referred to in case 1. 3. Write-through cache with write buffers. We present a simple approximate analysis here (generally accurate for low write traffic, r» 0.3 or less). There are two sub-cases in dealing with write buffers, depending on the type of buffer management protocol on a read miss: (a) On a read miss, the pending write buffer addresses are checked against the missed line address. If a match is found, the write is performed before the read. If no match is found, the read miss precedes (has priority over) all pending writes. (b) On a read miss, all pending writes in the write buffer are written to memory before the read miss is handled. For both sub-cases, assume that the write buffer is relatively large (no overflows) and the traffic is relatively lowlow mean queue size, hence insignificant read-write interlock delays (sub-case (a)). The write buffer allows write traffic to proceed at the offered rate, so there are no closed-queue slowdown effects. Now the analysis of sub-case (a) is exactly the same as case 1, assuming the probability of a match is low. The only delay to the read miss occurs because of already initiated but currently incompleted writes. Sub-case (b) introduces open-queue waiting time, as now the read request must wait in the queue until all pending writes are completed. From the Mb/D/1 open model: or, for our memory system: where In this sub-case, the overall write miss time is (assuming no fetch bypass): Tmiss = Twrite interference + Tw + Tc.miss, Where Tc.miss = Tline access. If fetch bypass is used, Tc.miss = Ta and an additional Tinterference must be added to Tmiss to account for read-read interference. This is the same as the Tinterference developed for the copyback cache.
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