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Page 408 If Probw is the probability of a write request in any processor cycle (Dt), then Prob (write during Tc) = Prob ( write during any of theTc/Dt cycles preceding a miss). Now Prob (no write in any specified cycle) = 1 - Probw and Prob (no writes in a sequence of Tc/Dt cycles) = (1 - Probw)Tc/Dt and Prob (a write in a sequence of Tc/dt cycles) = 1 - (1 -Probw) Tc/Dt. Finally, we (roughly) estimate the delay as Tc/2. So, The interference is independent of m, as the entire memory system must be available before the read miss can be handled. When the total write traffic (perhaps from multiple processors with writethrough cache) becomes significant with respect to the available memory bandwidth, additional contention analysis is required. 2. No write buffer, significant write traffic. This case offers an extension to case 1, since now the write traffic is significant enough to affect processor performance. Thus, the principal modeling assumption is that when memory contention arises as a result of memory write traffic, it is immediately reflected in a lowered offered write request rate, which affects the overall processor request rate. Imagine that processor requests are divided into two request streams: read and write. As seen by the processor, the read request rate is unaffected by memory contention. (The processor is blind to its idle time.) However, write requests are delayed by contention, so that if the total processor (offered) request rate is l, then: l = lr + lw, the sum of the offered read and write request rates. The achieved rate is la: la = lr + lwa. The achieved rate la differs from l by the decrease in achieved write traffic (lwa). We can compute lwa by finding B(m,nw). where nw is the effective mean number of write requests per memory cycle. Then
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