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6.8.7 Simple Write-Through Caches |
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The analysis of write-through caches largely follows that of copyback caches. There are two differences, however: |
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1. Tbusy is simpler, since no dirty line writes need be considered. |
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2. Writes that immediately precede a miss can delay the line access until memory is available. |
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For a processor that waits until the cache line is filled before resuming: |
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Tbusy = Tm.miss - Tc.miss = 0. |
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For the processors using fetch bypass, Tc.miss = Ta and |
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Tbusy = Tline access - Ta. |
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The modeling of memory and write-through cache interaction strongly depends on: |
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1. The existence of write buffers. |
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2. The policy of dealing with the write buffer contents on a read miss. |
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3. The amount of write traffic. |
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In the following, we consider some typical modeling cases: |
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1. No write buffer, low write traffic. |
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Here, we need only compute an interference time, since we assume that memory contention is generally negligible. Tinterference can then be computed, as in the case of copyback caches, but recall that the processor traffic (lp) now consists only of read traffic, since write cannot cause a miss. Writes that immediately (within Tc) precede a read miss occupy memory and delay the line access. For simplicity of discussion (and memory control), assume that all memory modules involved with a line access must be available before it can begin. Let us call the effect of these "writes before misses" Twrite interference.As with read interference, we need to compute: |
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Twrite interference = Prob (write during Tc given a read miss) delay factor. |
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