(c) Now we repeat the problem assuming both a dirty line buffer and wraparound load.
Here,
Tc.miss = Ta = 120 ns,
and
Tbusy
=
Tm.miss - Tc.miss
=
390 - 120
=
270 ns.
Then
(d) Repeat (c), including the effects of line-oriented I/O without processor preemption of pending I/O request. Again, all requests are for lines. Suppose the I/O traffic is 0.05 of the processor traffic (i.e., I/O fraction i = 0.05).
Since the ri is low, we estimate Tw-I/O using M/D/1 open queue:
