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Figure 6.26
Wraparound load. |
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1. On miss, write a line (if dirty), then read the complete line before the processor resumes. This is the case discussed previously. Here, we first write the altered (dirty) line to the memory, then read the new line into the cache, then resume processing. |
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2. On miss, write a dirty line to a write buffer while the new line is being accessed, then read in the new line. When the processor resumes, the dirty line is written back to memory. Now |
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More sophisticated caches access the faulted word first, then "wrap" around the accessing of the remaining words in the line. Processing resumes (as does referencing to the cache) as soon as the faulting word reaches the processor. |
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Tc.miss is defined as the time the processor is idle awaiting its first word from memory. With demand fetching, fetch-bypass, and wraparound load, Tc.miss is typically the same as Tathe access time to the faulted word, assuming a typical cache configuration (Figure 6.26). |
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Fetch-bypass is used to accelerate a demand fetch: when a miss occurs, the desired bytes are passed directly from the main memory to the processor, bypassing the cache. Here, the load of the cache proceeds simultaneously with the fetch-bypass. A wraparound load means that the transfer begins with the bytes accessed and wraps around to the rest of the line. |
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(1 + w) Tline access - Ta. |
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If the processor creates a miss during Tbusy, it encounters delay in addition to Tc.miss. This is not, strictly speaking, a queueing delay; rather, it is simply interference by the processor with one of its own overlapped operations. Suppose we designate this time as Tinterference. Then |
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Tinterference = Expected number of misses during Tbusy. (Delay per miss). |
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