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Figure 6.25
Computing line access time. |
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This is shown in Figure 6.25, and computed as: |
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6.8.3 Contention Time (Tbusy) and Copyback Caches |
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Consider a simple copyback cache (CBWA), where on a miss the processor does not resume until a dirty line (w = probability of a dirty line) is written back to memory and the new line is fully written in the cache. The miss penalty (Tmiss) or delay is: |
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Tmiss = (1 + w) Tline access. |
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If we ignore the effects of I/O, however, there is no possibility of memory contention for this simple cache! The processor ceases requests to memory when memory is busy and contention cannot develop. |
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Now, Tmissthe total ''effect" of a missmay be different for the cache than for the main memory. The processor may resume accessing the cache before the memory system completes processing the miss (e.g., writing back a dirty line). Let us distinguish between two miss times: |
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1. Tc.missthe time the processor is idle due to a cache miss (without interference/contention). |
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2. Tm.missthe total time the main memory system takes to process a miss (again ignoring contention). |
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We define the potential contention time (Tbusy) as the time memory is busy and the time the processor is enabled to make requests to memory: |
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Tbusy = Tm.miss - Tc.miss. |
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For copy back (CBWA) caches (ignoring I/O), we might have: |
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