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Figure 6.27
I/O contention. |
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Expected number of misses during Tbusy |
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number of requests during Tbusy Prob (miss) |
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where lp is the processor read request rate and f is the miss rate per request. |
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The delay factor given a miss during Tbusy is simply estimated as Tbusy/2, assuming a uniform miss distribution. Then |
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and the total miss time seen from the processor (excluding effects of I/O) is |
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Tmiss = Tc.miss + Tinterference. |
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For copyback cache (CBWA) and line buffered I/O, all references are to lines. If a cache miss immediately follows the beginning of an I/O line transfer, |
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Tbusy = Tline access. |
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Queueing delays (i.e., contention) arise whenever one of the following pairs of requests occurs (at the same memory module) within too short a time: CPU-I/O (CPU occupying channel, I/O requests service), I/O-CPU, CPU-CPU, or I/O-I/O. The CPU-CPU was previously handled by considering it as interference that the processor handles itself, and not as queueing contention/-delay. Cases I/O-I/O and CPU-I/O cause queueing delays at memory, and delay the I/O unit, but do not delay the processor. The first case, I/O-CPU, causes queueing delays (visible to the processor) that can be calculated. For a CBWA cache with line-buffered I/O, the I/O (word) request rate li is treated as if it were another processor, while Tline access is the service time Ts. We model the effect of I/O by assuming that the processor is "blind" to its own accesses and that it can only "see" the I/O effect on memory as causing contention. The I/O-CPU contention delay (as seen by the CPU) can thus be calculated as Tw-I/O. |
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In computing this contention, we have two request sources li from the processor-cache and li from the I/O system, but only li actually causes contention. The li request stream, however, can secondarily affect the |
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