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Assuming that Tbus is of the same order of magnitude as Tv, we would have: |
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This is generally similar in form to the interleaved case, with a minor adjustment for the Tbus, Tv distinction. |
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EXAMPLE 6.7 COMPUTING TLINE ACCESS |
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Assume we have Ta = 200 ns, Tc = 150 ns, Tv = 40 ns, Tbus = 50 ns, L = 8, and v = 4. |
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We would have the following time relationship: |
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The final case is an interleaved memory consisting of modules with fast sequential page mode. Assume |
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That is, that memory to processor transfers are determined by the bus time (Tbus), not the interleaved page time. |
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Here, the line access is approximately: |
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EXAMPLE 6.8 COMPUTING TLINE ACCESS |
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