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Tc plays a role for L > m, since the first accessed memory module may not be available when requested at the Tbus rate. |
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If Tc < (m) Tbus, even if L > m, the memory cycle is faster than the bus usage and the initial memory module has recovered before it is to be used again. Thus, we have: |
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Tline access = Ta + (L - 1) Tbus. |
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Now for L > m and Tc > (m)Tbus, the memory cycle time dominates the bus transfer. The result depends on the relationship between Ta and Tc, so a timing diagram is useful; but as an estimate, we can use |
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Assume that we have Ta = 300 nsec, Tc = 200 nsec, m = 2, Tbus = 50 nsec, and L = 8. We would have the following timing relationship: |
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The first word in the line is available in Ta, but that module is not available again until Tc. A total of  accesses must be made to the first used module, with the first access accounted for by Ta (assuming Ta > Tc). Thus, an additional  - 1 cycles are required. Finally, (L -1) mod m bus cycles are required for the other modules to complete the line transfer. |
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Now we assume a single module memory system (m = 1) with sequential page mode. We assume the memory has the following characteristics: |
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Ta, the access time to the first retrieved item. |
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v, the maximum number of fast sequential accesses that can be made to the module before a memory refresh time is required. |
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Tv, the minimum time between sequential accesses during page mode. |
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Tc, the cycle time assumed to be the same as the memory refresh time between accesses of v items in page mode. |
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Thus, we have the following relationship: |
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