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In the remainder of this chapter, we look at (1) single or split caches with either fully blocked, partially blocked, or nonblocking interactions with memory, and (2) interleaved caches. |
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As we will see, simple caches with either fully or partially blocked memory interactions can easily be modeled without using queueing theory. We model nonblocking caches in a manner similar to the treatment of multi-programmed processor-I/O systems. Finally, we model interleaved caches in much the same way we modeled interleaved memory systems. |
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6.8.1 Fully and Partially Blocking Caches |
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The addition of a cache to a memory system complicates the performance evaluation and design. For copyback systems with write allocate (CBWA), the requests to memory consist of line-read requests and line-write requests. For write-through systems without fetch-on-write (WTNWA), the requests consist of line-read requests and word-write requests. |
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In order to develop models of memory systems with cache, two basic parameters must be evaluated: |
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1. Tline access, the time it takes a cache to access a line in memory. |
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2. Tbusy, the potential contention time during which the memory is busy and the processor/cache is available to make requests to memory. |
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In the following sections, we discuss these parameters and then apply them to the evaluation of various caches. |
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6.8.2 Accessing a Line (Tline access) |
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We consider pipelined single processor systems. The usual memory arrangement for supporting fast line access involves the use of: |
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2. Fast sequential page mode. |
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3. A combination of the two. |
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We consider each of these arrangements in this section. |
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For our interleaved memory module analysis, we assume that the cache has a line size of L physical words. (The physical word is defined by the bus word size.) The memory is low-order interleaved to degree m, where m ³ L. The total time to move a line is given by: |
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Tline = Tline access = Tline-read = Tline-write = Ta + (L - 1) Tbus, |
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where Ta is the word-access time, and Tbus is the shared bus cycle time. (Usually Tbus is the same as the internal processor cycle time.) The memory system, while interleaved, does not begin to process a request until it is completely free. |
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