Note that n and m are unaffected and are computed as before.
Study 6.1 Using the d-Binomial Performance Model
Assume we have a processor with cycle time 40 ns. It makes a memory request each cycle according to the following probabilities:
Prob (IF in any cycle) = 0.6
Prob (DF in any cycle) = 0.4
Prob (DS in any cycle) = 0.2
The design execution rate is 1 CPI.)
Assume for each memory module Ta = 120 ns, Tc = 120 ns. In this study, we look at two different processor-memory modeling situations:
(a) Processor with interleaved memory.
Assume we use four-way Interleaving, m = 4. Computen:
The processor offers the memory system 3.6 requests each Tc but the memory system can deliver only 2.3. This has a direct effect on processor performance, since only 2.3 new requests are being honored each Tc.
The offered performance (1 CPI at 40 ns/cycle) is 25 MIPS, while only 16 MIPS is achieved due to memory contention.
