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(b) Simple processor with ideal (write-through) cache. |
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Assume we have the same processor as in (a), but now we have an idealno misses at allwrite-through cache. Only writes go to the memory system. We assume that the writes have only limited buffering and that processor performance is directly affected by memory write contention. (We will consider more complete cache models later in this chapter.) |
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Assume m = 2. |
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Compute n: |
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B(2,0.6,0.2) = 0.54, |
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so that write traffic is affected by |
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and write traffic is slowed down by 10%. Of course, overall processor performance is affected by a lesser amount. For IF and DF, there is no performance slowdown. Thus, the overall performance estimate is: |
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Perfachieved = .983(25) = 24.6 MIPS. |
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Notes: Part (a) illustrates that for many situations there may not be a great difference between the simple binomial model B(4,3.6,d = 1) = 2.45, and the d-binomial model (a 6% error). Part (b) of this study illustrates the case where n < 1 and d is small. Using the simple binomial model under such conditions produces significant error (> 20%). |
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