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Figure 6.23
The pipelined processor. |
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To simplify the analysis, we assume that (1) the pipelined processor consists of multiple independent request sources (IF, DF, etc.). Only one request can be made by a source each cycle, and if multiple requests are made the processor randomly selects one and rejects the others. (2) the probability of a request in any cycle is independent of actions in the previous cycles (Figure 6.23). This second assumption certainly introduces some error into our analysis, as requests delayed in one cycle affect the requests in the next cycle. Still, for many processor design situations these are reasonable assumptions, since d is usually not a strong determinant of performance. |
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Now we can compute d, the probability that any given source makes a request. |
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First, the number of sources (z) is: |
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where cr is the number of processor sources making requests each processor cycle (Dt). Typically, cr consists of a DF (data fetch), IF (instruction fetch), and DS (data store buffer). If a "source" makes more than one request per processor cycle (e.g., IF can be an in-line request plus a TIF), then it is treated as multiple sources. Each source can make only one request per processor cycle (Dt). |
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where n is the previously discussed mean number of requests per Tc (or, more generally, service time). |
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Suppose a pipelined processor has three request sources that contend for access to memory each machine cycle (Dt). These sources have discrete probabilities of: |
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Suppose there are three processor cycles per memory cycle; then |
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z = 3 ´ 3 = 9 |
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