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Analyzing Interleaved Memory Systems |
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At first glance, it may seem that analyzing a processor (without cache) connected to an interleaved memory system is something of an anachronism. Yet the processor interleaved memory model is the building block for the analysis of any complex memory system. In the remaining sections, we extend this model to include processors with cache and eventually to multiple processors in various shared memory arrangements. Moreover, as processors get faster, and caches get larger, there will be a need to improve the cache-processor bandwidth. This need can be satisfied most simply by interleaved caches, whose performance analysis follows interleaved memory. |
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where B is the achieved queue size in the buffer (per module). Now, since n/m = r, the offered occupancy is the same as the achieved occupancy (pa) so long as B is less than the actual buffer size, (BF), r = ra, since |
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There is a critical occupancy (pc) at which the mean buffer size approaches the physical buffer size. Suppose |
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To a first approximation, the system acts as an open-queue system so long as rc > r, then as rc < r the queue saturates and behaves as a closed-queue system. |
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While the above is generally descriptive of buffered closed queues, it is analytically simplistic and inappropriate for general use. The problem is that a queue of mean size B (B < BF) may momentarily have queue > BF. This slows the system down well before r = rc. |
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We call systems that are tolerant of some system delay (waiting time) or have some buffering of requests mixed queueing systems. We will look at appropriate models for such systems in chapters 7 and 9. |
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