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Figure 1.17
Instruction size for various instruction formats L/S and R/M. |
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Figure 1.18
Assumed instruction size for differing formats for the R+M architecture.
Current examples of R+M machines use byte-variable instructions (VAX,
M680x0, etc.). For our purposes, we assume a simpler R+M instruction
layout of four basic sizes, 16 through 64 bits, differing by the number of
memory (or literal) specifiers required. In dealing with R+M byte-variable
instruction sets, the reader should interpret the preceding sizes as the
expected instruction sizes for each of the indicated formats. |
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