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instructions are a single word (32 bits) in size. In R/M, the source and destination are the same register, designated Rds1. The R+M includes many more formats; the variety is shown in Figure 1.18. In Figures 1.17 and 1.18, the address represents space for base and index register indicators as well as a memory address or offset value.
Even when the format is known, other details, such as the operand addressing mode, may in actual situations determine an instruction's size. For example,
d87111c01013bcda00bb8640fdff6754.gif
OP R1, [R2]
may in some R/M or R+M machines be representable in a 16-bit RR format while in other machines be (implicitly) representable as
d87111c01013bcda00bb8640fdff6754.gif
OP R1, 0[R2]
that is, in a 32-bit R/M format. We usually assume that such non-direct register mode requires the "RM" format. Thus, in an R/M machine,
d87111c01013bcda00bb8640fdff6754.gif
OP  R1, [R2]
OP  R1, #valve
LDA R1, disp[R
base, Rindex]
all require the 32-bit RM format. The LDA instruction simply loads the indicated address into R1, where disp indicates an address displacement, Rbase a base register, and Rindex an index register.
1.6 Addressing and Memory
Addressing in modern machines consists of several levels of address mappings [69, 70, 161]. Each level (the user program, the operating system, or the hardware manager) provides special services for the user.
Generally, we can describe three levels of addressing (Figure 1.19):
1. The process or user program level. At this level, the primary concern is with the efficient representation of user statements.
2. The system level. The primary concern is with multiple processes sharing a fixed address space. Issues include relocation and protection.
3. The memory level. This is the set (or sets) of physical locations used to interpret level 1 and 2 addresses. The primary concern is with access time. A memory manager is responsible for the prediction of localities (or working sets) that are about to be used so that they can be readied (accessed) by the processor.
1.6.1 Process Addressing
The designer must provide the user with facilities for efficiently addressing a large number of objects. In almost all modern processors, the basic

 
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