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1. An instruction that explicitly calls another module. |
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2. A trapan unusual data condition that arises during the course of the execution of a module and that implicitly calls the operating system or a service module. (Also, special or undefined opcodes can be used as traps to support particular operating systems functions.) |
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3. An interrupta concurrently executing process module or an external event that notifies the executing module of an event of mutual interest. For example, the power supply system may be able to notify (interrupt) a program several milliseconds before power fails, allowing some measure of data recovery. |
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For our purposes, we are concerned only with the control that the instruction set exercises on the sequencing of modules to realize program execution. The simplest type of program transfer is branch and link (BAL) in System/390 or branch to subroutine (BSB) in VAX. In either of these instructions, the program counter is saved in a designated register and an unconditional branch is executed to a destination specified in the instruction. |
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A generalization of this is a call instruction found on VAX (CALLG). Not only does control pass to a new location, but an argument list is also specified in the instruction in the form of a pointer. This points to the first of several arguments that have been prepared by the calling module for use by the caller. In SPARC, the passing of arguments is accomplished simply by moving a register window. As will be discussed later, windowing consists of a series of overlapping register sets within which arguments are prepared by the calling module. These arguments are prepared in the upper end of the caller's register set space; when control passes, these same registers become the lower part of the callee's register set. |
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Frequently a user procedure must call on the operating system for service: e.g., request for additional memory, a call to the supervisor, or a call causing a change of mode (kernel executive, supervisor, user). |
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Usually, most architectures are more similar than different insofar as their control structure is concerned; the differences that do exist reflect the amount of information contained in the PSW, or the number of states available to distinguish among users and various levels of protection. |
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Program size (static or dynamic) is determined by the number of instructions involved and the size of each instruction. The type and variability of instruction formats play a key role in both of these qualities. Figure 1.17 shows the various instruction sizes assumed for each of the prototypical architectures used in the text. Our R+M prototype is only a rough approximation of a machine such as a VAX, whose instruction size is byte-variable from 1 to 19 bytes! |
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We designate each format by the number and types of addresses it specifies. Thus, the L/S architecture has two basic formats: RRR (specifying three distinct registers for an ALU operation) and RM (specifying a register and a memory address, perhaps including offset and base register). All L/S |
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