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and then return to the original bit address. |
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In page mode, a single row is selected and nonsequential column addresses may be entered at a high rate by repeatedly activating the CAS line (similar to nibble mode, Figure 6.5). |
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While terminology varies, nibble mode usually refers to the access of (up to) four consecutive words (a nibble) starting on a quad word address boundary. Chips that feature the retrieval of more than four consecutive words sometimes identify this feature as fast page mode. To avoid confusion, we use the term sequential page mode for sequential addresses and simply page mode for chips that allow nonsequential accesses. |
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Since new addresses do not have to be entered in nibble mode, it gives somewhat faster access than page modehowever, page mode allows greater flexibility in addressing multiple words in a single address page. As an example of page mode, consider if we initially had row address 723 and column address 424; then entries with the same row and any other column address could be rapidly accessed in page mode. |
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Particular memory chips are equipped with nibble mode, with page mode, or with neither. (See Appendix D.) In the design of the memory module, the designer must consider the various available options in order to achieve the desired transfer rate. For the remaining discussion on non-cached processors, we treat the memory system as if it were a system composed of individual memory modules, usually without either nibble or page modes. In fact, nibble mode and page mode provide alternate ways of realizing multiple memory modules and the designer must take these into account in achieving overall design effectiveness. |
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Organizing the Memory Chip |
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As the capacity of memory chips becomes increasingly large, the conventional arrangement of organizing a chip 2n´ 1 bit becomes increasingly untenable. For a 16-megabit chip, organized 16 M ´ 1b, a single module with a 64-bit physical word size would contain a gigabit (128 megabyte) of storage. Interleaving modules of such size becomes expensive, to say the least! |
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For memory bandwidth, the techniques are twofold: using chips organized 2n´ p¢ bits, and using fast page mode (Appendix D). The first technique allows for a smaller memory module; for example, the 16-megabit chip could be organized 4 million ´ 4 bit, reducing the module size (64 bit physical word) to 32 megabytes. The second technique can, in many cases, eliminate the need for interleaving. |
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6.2.2 Error Detection and Correction |
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Most modern memory systems are implemented with high-density dynamic RAM cells. Each storage cell consists of a transistor that contains charge, representing the state of the cell. In an effort to improve density, these cells are shrunk in size to the limits permitted by lithography and reliable operation. Extremely small amounts of charge then determine whether or not the |
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