|
|
|
|
|
|
|
Figure 6.7
Two-dimensional ECC. |
|
|
|
|
|
|
|
|
state of a cell is either one or zero. Small environmental perturbationsstatic electric discharge, alpha particles, etc.may impinge on a cell, changing its state. Altered charge in a cell represents corrupted dataan error. Since these errors are a natural consequence of the type of technology used in memory design, they must be compensated for within the system design itself. |
|
|
|
|
|
|
|
|
The simplest type of error detection is parity. To every physical memory word a bit is added (a check bit), which ensures that the sum of the number of 1's in the word is even (or odd, by predetermined convention). If a single error occurs to any bit in the word, the sum modulo two of the number of 1's in the word is inconsistent with the parity assumption, and the memory word is known to have been corrupted. |
|
|
|
|
|
|
|
|
Knowing that there is an error in the retrieved word is valuable. Often, a simple reaccessing of the word may retrieve the correct contents. However, often the data in a particular memory cell has been lost and no amount of reaccessing can restore the true value of the data. Since such errors are likely to occur in a large memory system, most modern memories incorporate hardware to automatically correct single errors (ECCerror correcting codes). |
|
|
|
|
|
|
|
|
The simplest code of this type might consist of a geometric block code. The message bits to be checked are arranged in a roughly square pattern, and the message is augmented by a parity bit for each row and for each column. If a row and a column indicate a flaw when the message is decoded at the receiver, the intersection is the damaged bit, which may be simply inverted for correction. If only a single row or a column or multiple rows or columns indicate a parity failure, a multiple-bit error is detected and a non-correctable state is entered. |
|
|
|
|
|
|
|
|
For 64 message bits, we need to add 17 parity bits: eight for each of the rows and columns and one additional parity bit to compute parity on the parity row and column (Figure 6.7). |
|
|
|
|
|
|
|
|
It is more efficient to consider the message bits as forming a hypercube, for each message combination forms a particular point in this hypercube. If the |
|
|
|
|
|
