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Figure 6.3
Accessing delay in a complex memory system. Access time
includes chip accessing, module overhead, bus transit delays,
etc. |
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The memory module is the building block for the memory system. Throughout this chapter, we usually treat it as a unit. However, in this section we look inside a DRAM (dynamic random access memory) module to understand issues such as chip configuration, operation, and timing and their relationship to the overall operation of a module. |
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DRAM differs from SRAM (static random access memory) in the following ways: |
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1. The SRAM bit cell uses multiple transistors to hold information. It remains in a stable state as long as power is on. The DRAM cell usually consists of a single transistor and capacitor. The state of this cell must be refreshed at regular time intervals. |
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2. As a consequence of (1), these cell designs have evolved in significantly different ways. The SRAM is less dense than DRAM (usually less than one-hundredth the density), but has much faster access and cycle times (perhaps one-tenth the cycle time). |
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With the exception of certain supercomputers, almost all modern memory modules are composed of the DRAM chip. The DRAM chip is usually organized as 2n´ 1 bit, where n is an even number. Thus (in 1994) the one-megabit chip (220´ 1) and the four-megabit chip (222´ 1) are common commodity memory chips. |
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Why an even power of two? Internal to the chip is a two-dimensional array of memory cells consisting of rows and columns. Thus, half of the memory address is used to specify a row address, one of 2n/2 row lines, and the other half of the address is similarly used to specify one of 2n/2 column lines (Figure 6.4). The cell itself that holds the data is quite simple, consisting merely of an MOS transistor holding a charge (a capacitance). As this discharges over time, it must continually be refreshed (i.e., recharged) on a regular basis, approximately once every four milliseconds. |
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