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In this chapter, we begin with the study of the basic memory module and its characteristics. Section 6.3.2 covers the solution of "classical" memory contention where n simple processors access m interleaved memory modules. Since modern processors are buffered and allow out of order accessing of data, the classical models are of limited value in systems analysis. We introduce queueing models in section 6.4 that are adequate for the solution of most simple design situations. Finally, we look at modern pipelined processors with various types of cache configuration and their effect on the memory system. |
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The memory models presented here are basic to understanding more advanced processor configurations. Thus, the queueing models presented in this chapter are the basis for understanding the performance of vector processors presented in chapter 7 and multiprocessors presented in chapter 8. Queueing models are also invaluable in the analysis of I/O systems as discussed in chapter 9. |
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The performance of almost any system is dependent on the performance of that part of the system with the least capacity. If the basic processor has the least capacity then our analysis of processor performance as discussed in the preceding chapters is sufficient to understand the performance of the entire system. This is usually not the case, however. Either the memory, or the network which accesses the I/O system, or the I/O processor, or the I/O devices themselves typically represent the capacity bottleneck in the system. Ultimately, it is this bottleneck that determines overall systems performance. Fortunately, the basic queueing models discussed in this chapter can give us a great deal of insight into the analysis of and effect of these capacity bottlenecks. |
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Each memory module has two important parameters: module access time and module cycle time. The module access time is simply the amount of time required to retrieve a word into the output memory buffer register of a particular memory module, given a valid address in its address register. Memory cycle time is the minimum time between requests directed at the same module. Various technologies present a significant range of relationships between the access time and the cycle time. The access time is the total time for the processor to access a word in memory. In a small, simple memory system (equivalent to a single module), this may be little more than chip access time plus some multiplexing and transit delays. The cycle time is approximately the same as the chip cycle time. In a large, interleaved memory system (Figure 6.3), the access time may be greatly increased, as it now includes the module access time plus transit time on the bus (two directions), bus accessing overhead, error detection and correction delay, etc. The cycle time (for the module) remains the same. In general, the designer should not be surprised to find system access times that are less than, equal to, or greater than the cycle time of a particular module, depending on the complexity of the system. |
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