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In the simplest possible arrangement, a single simple processor makes a request to a single memory module. The processor ceases activity and waits for service from the module. When the module responds, the processor resumes activity. Under such an arrangement the results are completely predictable. There can be no contention of the memory system, since only one request is made at a time to the memory module. Now suppose we arrange to have n simple processors access m independent modules. This arrangement represents a classic study in computer systems analysis. Contention develops when multiple processors access the same module. Contention results in a reduced average bandwidth available to each of the processors. Asymptotically, a pipelined processor making n requests to the memory system during a memory cycle resembles the n processor m module memory system, at least from a modeling point of view. But in modern systems, processors are usually buffered from the memory system by cache. Whether or not a processor is slowed down by memory contention during cache access depends a great deal on the cache design and the number of processors that share the same memory system. To a first approximation, a single pipelined processor with a copyback cache is unaffected by bus or memory contention. The overall system is usually affected but slightly for a write-through cache. |
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As we shall see in the next chapter, the performance of vector processors can be significantly affected by bus or memory contention. Similarly, multiple cached pipelined processors are also directly affected by bus or memory contention. |
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Using multiple memory modules to provide sufficient memory bandwidth to the processor is a standard technique. |
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Most analyses of performance of interleaved memory systems assume that address requests are uniformly distributed across the modules. In many situations, address requests tend to be sequential; in fact, performance analyses of memory systems based upon a uniformly distributed address request pattern generally provide a conservative estimate of performance when the actual pattern is largely sequential. |
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References to vectored data structuresnonsequential systematic address referencesare the nemesis of the memory system designer. If the vectors are long enough and the address distance between successive references is great enough, a data cache will be virtually useless; worse, it may create significant additional traffic, further slowing down the memory system. Yet techniques are available for organizing the memory system to provide reasonably robust performance for vector address references. The designer must anticipate such an application requirement during the design of the memory system. |
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