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Figure 6.2
Achieved memory bandwidth as a function of the
offered request rate. |
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the number of requests directed at each individual module and, correspondingly, the congestion and delay experienced at each module. Although this is generally true, certain highly structured reference patterns can result in anomalous behavior. |
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The offered request rate to the memory system is the rate at which the processor would be submitting memory requests if the memory had unbounded bandwidth and processed the requests without contention. The offered request rate establishes an upper bound on the achieved memory bandwidth. Another upper bound on the achieved bandwidth is the theoretical maximum memory bandwidth, which is determined by the cycle time of the memory and the number of memory modules. The achieved bandwidth, as a function of the offered request rate, initially is equal to the offered rate. As the offered rate increases further, the achieved bandwidth continues to increase, but not as fast, and it levels off asymptotically at the theoretical maximum bandwidth. (See Figure 6.2.) Aside from this overall behavior, the detailed dependence of the achieved bandwidth upon the offered request rate varies depending on a host of other factors. |
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The offered request rate is not influenced by the organization of the memory system. In the absence of cache, the factors that affect it are the instruction set architecture of the processor, including register set size and organization, the nature of the program currently executing on it, and the organization of the processor. As discussed in chapter 2, an instruction set architecture that provides a general-purpose register set can be expected to generate fewer memory requests per instruction executed than would a memory-to-memory architecture. Assuming an architecture of the former type, a program that made more effective use of the registers would offer a lower request rate to memory. The processor organization affects the offered request primarily through its speed, but factors such as prefetch of data and conditional execution of instructions following a branch increase the number of references per instruction and thus have an effect as well. |
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The modeling and analysis of memory contention is strongly dependent on the complexity of the processor making requests to memory and on the number of processors that request service from a common shared memory system. |
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