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Page 331 while split cache would degrade performance by: .03 ´ 1 ´ 6 + .044 ´ 1 ´ 6 = .44 CPI. In the context of the study 4.3 result of 2.82 CPI (without cache miss), the difference between cache approaches is limited to less than 5% and we might well select the simpler split cache approach. While we assume a split I/D implementation for the rest of this study, we have simply made estimates at this point and these must be carefully checked later. 5.18.1 Actual Reference Traffic Now we return our attention to computing the actual reference activity from the processor to the cache (memory system). We need to know the total traffic or references per instruction as well as the constituents of this traffic. This allows us to compute the exact cache miss rate and to make required design tradeoffs between cache and memory. The processor traffic has three constituent parts: 1. Instruction references/instruction. 2. Data (read) references/instruction. 3. Data (write) references/instruction. Given the parameters of the problem (R/M instruction set, 8-byte physical word size), we know the I-references/instruction to be 0.73 from the computation on page 313. Similarly, from the data in Table 5.7, we know the data (read) references/instruction to be 0.34 and data (write) references/instruction to be 0.21. Cache Design After the traffic evaluation, the design of the cache is rather straightforward. Notice that an actual traffic rate of 0.73 I references/instruction is similar to that used in the earlier evaluation of miss rate, while the D read references/instruction is significantly lower. The effect of actual traffic on performance is: 0.03 ´ .73 ´ 6 + 0.044 ´ 0.34 ´ 6 = .22 cycles, which is well under 10% of the estimated execution time per instruction. We select the conventional cache attributions, stressing low cost. For Icache, We select: Size: 32KB Organization: set associative degree 2 Replacement: random No writes (I-cache)
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