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Also assume a user plus system environment (where the system includes the effect of I/O). |
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The instruction timing layout is similar to study 4.3: |
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The total cache access requires two cycles (i.e., increasing it from 65ns to 100ns) in order to match cycle boundaries. |
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We know from study 4.3 that an average instruction takes 2.82 cycles, but the cache should be designed so as not to be limited by cache bandwidth. The processor activity is dominated by bursts of execution at the maximum rate separated by delays due to branches, etc. The design should be limited by the more expensive facilities. For this study, we assume that the cache is not such a limiting facility. |
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Since two requests (one instruction, one data) may simultaneously be directed at the cache, a fundamental consideration in cache design is whether to integrate data and instructions in a single cache, or to split references into separate caches. The split cache is simpler to implement and more readily accommodates two requests/cycle, but the integrated cache has a lower miss rate. |
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Assuming two-way set associativity, from Figure 5.10 we can estimate a worst-case miss rate of about 1.8% for an integrated 64KB cache in a scientific environment, ignoring the details of the cache organization. This is increased by a factor of 1.70 due to systems effects (Figure 5.22), giving an overall miss rate of 3.1%. |
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Now, the simplest cache to implement would be a split I/D cache, each of 32KB with no duplicate entries allowed. From Figures 5.28 and 5.29, this gives us: |
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Taking the system (and I/O) into account, we have: |
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Since the total references per instruction cannot exceed two (one for instruction and one for data), and the cache miss penalty is unlikely to exceed 6 cycles, we can estimate the performance degradation effect of an integrated design as miss rate ´ references per instruction ´ miss penalty: |
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0.031 ´ 2 ´ 6 = .37 CPI; |
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