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Figure 5.52
Mean misses per instruction (MPI) for a standard cache
(4KB pages, single LRU free page list) relative to the MPI
for a colored cache vs. cache size for three sample
programs (16B lines, unified cache). Data from Lynch
[188]. |
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as memory becomes fully occupied, of thrashing in the memory. The net effect of this is to reduce the effective memory size somewhat. Based on a number of program simulations, Lynch [188] has shown that this effect is minimalprobably less than a 1% effective reduction in memory size. |
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Is the loss of (say) half a megabyte out of 64 megabytes reasonable, in light of the improved cache access time and relative miss performance? Here again, the designer must use careful judgement in selecting the strategies suitable for a particular environment. |
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Design a cache for a 20 MIPS (peak) R/M-type CPU, used in study 4.3, with the following parameters. |
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Cache miss = 300ns (6 cycles) |
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Cost and memory considerations dictate a cache of 64KB with 32B lines and an 8B memory-cache transfer path (i.e., 8B is the physical memory word size). |
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For the cache data storage, assume Taccess = 50 ns, but that the total Taccess = 65 ns, including compare, multiplex, and transit delay to processor register. |
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