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Figure 5.51
T/DF overlap with colored pages. |
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The first approach requires the cache to be purged when a new process is entered. This might be satisfactory for small caches, but is limited as the cache size increases. The second approach increases the size of the cache directory but otherwise gives reasonable performance. |
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Either approach requires special attention to I/O, since I/O addresses are usually referenced to the real memory address space. In order to manage the I/O problem, certain areas of memory may be defined for which the virtual and real address spaces are the same. In this case, the I/O would use this space exclusively. |
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5.17.3 Physically Addressed Caches Using Colored Pages |
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Only a few virtual bits need go through the TLB before the cache access is made. We call these bits the color bits. The operating system (memory manager) chooses the real page address from a list of available pages (the free list) when a page miss occurs. By maintaining several free lists, one for each color bit combination, we can force the address bits required for cache access to always be V = R, i.e., have the same real bit address as virtual address. The remaining (upper) virtual address bits still must go through the TLB and be checked, but, as in approach (a), the cache access can occur concurrently with this TLB access. (See Figure 5.51.) |
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When the real page address is a function of the virtual page address, it is referred to as a colored page. Instead of adding additional hardware to maintain high degrees of set associativity, we accomplish the same effect in software by maintaining multiple free lists for page assignment. |
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Using colored pages has an added bonus: it reduces the cache performance variance caused by differing relative page assignments on different program runs when allocated off a (randomly assigned) single free list. Figure 5.52 illustrates the effective random assignments on an I-cache compared to a cache using colored pages. A colored physical cache gives the same relative performance as a virtual cache. I-caches are particularly sensitive to page relationships and assignments; hence, the random assignment usually produces a much poorer performance than the original address assignment (as in the virtual address), since the program is generally sequentially moving across its pages. |
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It seems nothing comes without a price, including page coloring. Main memory is now partitioned into 2b sets, where b is the number of low-order page number bits that are colored. Page allocation must now be accomplished from multiple correctly colored free lists. Since memory is now partitioned into classes or bins by the free lists, there is a higher probability, especially |
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