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Figure 5.50
Virtual-to-physical address translation. |
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case of 4KB pages, the lower 12 bits are unaffected by translation; thus, for up to 4KB caches, the TLB and the cache may be accessed simultaneously, since the cache index bits are known. Of course, before the accessed cache word can be forwarded to the processor, the cache directory must be compared with the output of the TLB to validate that the correct word has been accessed. As caches get larger, one approach has been simply to increase the degree of set associativity. For example, an 8KB cache with two-way set associativity still uses only the lower 12 bits to reference cache information. For larger caches, this rapidly becomes impractical; a 64KB cache requires 16-way set associativity. Notice that there is little or no advantage in a miss rate above about four-way set associativity. |
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Most caches buffer information exactly as it has been stored in memory. A real address is computed before accessing the cache, and real addresses are used as tags in the cache directory. This requires the translation of virtual addresses into real addresses (via the TLB) prior to accessing the cache. In a virtual cache, when a miss occurs, that address is then translated into a real address and the line is accessed from main memory. This introduces additional complexity, however. Now two processes may use different addresses to access the same real line, or the same address to access different real lines. For example, it is common for a process to be coded relative to address 0.00. These addresses will be assigned to different segments and different pages but their virtual addresses are the same. These addresses are referenced as aliases. Thus, it becomes important to distinguish among processes that might simultaneously reside in a single cache, or simply to prohibit multiple processes from occupying the virtual cache at the same time. There are two basic control strategies here: |
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1. To prohibit any process aside from the operating system to cohabit the cache at the same time as a user process. |
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2. To require a process ID number (PID) to be associated with each line in the cache directory. This uniquely determines the mapping from a virtual address to a real address. |
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