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Figure 5.49
Instruction address translation. |
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5.17.1 Set Associative Caches |
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In simpler processors the instruction timing template allows for sequentially executing the events: |
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AG ® T ® DF (cache access), |
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where T represents the V ® R translation using the TLB. The IF usually is simpler: |
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IA ® IF, |
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where the T is implied as part of the IA. This is possible since the IA generates an address outside the current page only infrequently (even on most branch target addresses, 80% lie within a 4KB page). Thus, in IA the result need only be checked, perhaps during IF, to ensure that it lies within the same (previously translated) page (Figure 5.49). |
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The DF is a different case, as the result of the data AG frequently lies outside its previous page. Thus, for DF the ordinary process is: |
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AG ® T ® DF. |
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So long as the cache size is equal to or less than the page size, we have (set associative and direct mapped) |
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AG ® T/DF, |
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since the bits needed to address the cache line (index bits) are those (lower-order) bits that do not need translation. The tag bits require the TLB access but the cache data can be accessed at the same time as the TLB access. |
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For direct-mapped caches larger than the page size, translated bits are needed for the index and hence to address a line in the cache. |
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In some processors, set associative caches of high degree have been used to allow parallel access to cache and TLB. Figure 5.50 shows the virtual-to-real address translation process. The virtual page offset identifies a byte in a page and, as mentioned earlier, is unaffected by TLB and translation. In the |
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