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Figure 5.45
TLB with two-way set associativity. |
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in the real address space, when they draw pages whose lower page address bits (and upper cache address bits) are identical. |
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The organization of this section is summarized in Table 5.9. |
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Excess not-in-TLB translations can generally be controlled through the use of a well-designed TLB. The size and organization of the TLB depend on the desired performance. |
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5.16.1 Translation Lookaside Buffer (TLB) |
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The translation lookaside buffer (TLB), as described in chapter 1, is closely associated with the cache. It provides the real addresses used by the cache by translating the virtual addresses provided by the processor into real addresses. |
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Figure 5.45 shows a two-way set associative TLB. The page address (the upper bits of the virtual address) is composed of the bits that require translation (a byte within a pagethe lower 12 bits for a 4KB pageis unaffected by translation). Several of the virtual address bits are used to directly address the TLB entries. These are usually not simply the lowest order except the virtual address, but rather selected (or hashed) from the bits of the virtual address. Hashing the bits of the virtual address is sometimes done to avoid too many address collisions, as might occur, for instance, when both address and data pages have the same, say, "000," low-order page addresses. The size of the virtual address index is equal to log2 t, where t is the number of entries in the TLB divided by the degree of set associativity. When a TLB entry is accessed, a virtual and real translation pair from each entry is accessed. The virtual addresses are compared to the virtual address |
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