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| Table 5.10 Some TLB data (published/reported data). |
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Figure 5.46
Not-in-TLB rate. |
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tag (the virtual address bits that were not used in the index). If a match is found, this match controls the MUXing of the corresponding translated real address to the output of the TLB. |
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The TLB access is integral with the cache access for fetching information into the processor. When a translation is not found in the TLB, the process described in chapter 1 must be repeated to create an accurate virtual-to-real address pair in the TLB. This may involve 15 to more than 30 cycles; TLB missescalled not-in-TLBare costly to performance. TLB access in many ways resembles cache access. Fully associative organization of TLB is generally too slow, and therefore set associative TLB is generally preferred. Some TLB organizations and TLB miss rates are shown in Table 5.10. |
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We use general cache DTMR together with cited data (Table 5.10) to create a TLB design target miss rate (Figure 5.46). |
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